Field of the Invention
This invention relates to an integrated circuit device incorporating internal logic and/or memory circuitry and, more particularly, relates to an integrated circuit device which can accept inputs at the levels of different logic families and which can provide outputs at the levels of different logic families.
In the development of semiconductor devices, separate logic families have developed. Using bipolar processes, the following logic families have developed: transistor-transistor logic (TTL), integrated injection logic (I.sup.2 L) and emitter-coupled logic (ECL). Using metal oxide semiconductor fabrication processes, both MOS and CMOS logic families have developed. Each logic family has its own circuit building blocks and operating parameters including set reference voltage levels and specified ranges of voltages, the so-called "levels", which signify the digital information, e.g. whether a digital "1" or a digital "0" is to be signified by the state of the device. The conventional approach has been to design an integrated circuit using a particular logic family to carry out logic or memory functions. Thus, a CMOS circuit would have signals supplied to it which were suitable to match the internal signals within the device; the output would also have a CMOS format. Similarly, an ECL circuit would have input voltages within the ranges which would specify uniquely the information being provided; the output would also be supplied in an ECL format.
Transistor-transistor logic was one of the earliest logic families and has been widely adopted for integrated circuit design. It remains a very pervasive logic family. As a consequence, in order to obtain compatability with TTL circuits some circuits designed with logic families other than TTL are provided input translators and with output translators which make the circuits look like TTL circuits. For example, some CMOS circuits are made to appear as TTL circuits. Also, so-called pseudo-ECL devices have internal ECL circuitry yet look externally like TTL devices. The AMD 29116 Microprocessor and the AMD 29501 Programmable Signal Processor are pseudo-ECL devices. Such devices are effectively high performance TTL devices and do not allow different logic circuit families to be used together on the same circuit board.
As the level of integration and degree of sophistication of semiconductor devices has increased, circuit designers have selected their circuit building blocks from parts based on different logic families. This has been due to the availability of complex logic functions and/or dense memory arrays in all of these various logic families. As a consequence, it has been necessary to provide external translators which would translate, for example, the output of a TTL chip to an ECL voltage level so that an associated ECL chip would receive an input that it could recognize. The Signetics 10124 TTL to ECL translator is such a part. Conversely, the output of an ECL chip may have required translation to a TTL logic level for an input to a TTL chip.
Emitter-coupled logic (ECL) gates are widely utilized for high-speed data processing, digital communication and test equipment. ECL offers high speed-power products and has the shortest propagation delay of any logic form. As a consequence, many high performance circuits are being designed with internal ECL logic. This internal logic may be required to receive inputs from or provide outputs to, for example, MOS or TTL devices. Or, an ECL chip may receive inputs from or provide outputs to an I.sup.2 L based logic device. Rather than use external translators which waste power and which add delays which work against the inherent short propagation delays of the ECL logic, it is greatly desired that on-chip translation capabilities be provided. The need for translation is due to the unique logic levels for each family. In the ECL logic scheme a voltage more positive than -0.8 volt is considered to be a logic "1", while a voltage more negative than -1.6 volts is considered to be a logic "0". In the TTL logic family a voltage greater than +2 volts is considered to be a logic "1" while a voltage less than +0.8 volts is considered to be a logic "0". Within integrated injection logic devices, a logic "1" is specified as a voltage greater than V.sub.BE and a logic "0" is specified as a voltage less than V.sub.SAT. For CMOS a digital "1" is V.sub.CC and a digital "0" is ground. For any given application there may be a preference for performing logic or storing memory using one particular logic family. Or there may be a need to mix several logic families on one chip. In either case multiple on-chip translators would be desirable to permit mixing and matching. Since there is a preference for obtaining high performance by utilizing internal logic functions with ECL logic, the on-chip translation scheme of the present invention will be described in the context of an integrated circuit device having ECL internal logic which receives inputs in several logic families.